A problem confronting digital integrated circuit designers today is obtaining high speed operation from a logic or memory circuit having a large capacitance in parallel with the output node. For example, large signal currents are presently required at the output node of a dot or of multiple input ANDs embodied in an FET integrated circuit, in order to charge the inherent capacitance in parallel with the node to a sufficient level to obtain a useable output voltage swing. The large signal current in turn generates substantial resistive power dissipation in the circuit, which is objectionable in high density applications. Reducing the signal current increases the signal transition times and propagation delay for the circuit. What the prior art needs is a means for extracting a relatively small signal current which appears in parallel with a large capacitance at the output node of an integrated FET logic or memory circuit, so as to transform it into a relatively large voltage signal for use in subsequent signal processing.